It is well known that in optical communication systems conveying digital information, whether the digital information is transmitted as single signal at a single carrier wavelength or as multiple signals at different carrier wavelengths (i.e., wavelength-division multiplexing), for a fixed bit rate per carrier wavelength, it is beneficial to design the transmitted signal to have a narrow optical spectrum. The narrow optical spectrum allows two wavelength-division-multiplexed channels close to each other, and usually provides more tolerance to the chromatic dispersion of the optical fiber.
Numerous patents and research papers have documented the use of on-off keying with duobinary filtering in optical communication systems. All of these works have utilized precoding to permit symbol-by-symbol detection without error propagation. While those works have described many different techniques to implement precoding, duobinary filtering, and modulation of the duobinary signal onto the optical carrier, all of these techniques result in transmission of equivalent optical signals, which take on one of three possible electric-field amplitude values, e.g., {−a, 0, a}. With a precoder, it is possible to recover the transmitted information bits by performing symbol-by-symbol detection on a signal proportional to the received optical intensity, such as the photocurrent in a direct-detection receiver. This technique also narrows the optical spectrum by about a factor of two as compared to on-off keying.
FIG. 1 is a block diagram illustrating a precoder 1 and a duobinary filter 2 as implemented in a transmitter in a conventional optical duobinary transmission system. To facilitate symbol-by-symbol detection, as shown in FIG. 1, the precoder 1 is used before the duobinary filter 2. Between the precoder 1 and the duobinary filter 2, the level shifter (L/S) 3 changes a logic value of “1” to a positive amplitude value of a/2 and a logic value of “0” to a negative amplitude value of −a/2. The precoder 1 is formed by an exclusive-OR (XOR) gate circuit 10 and a one-bit delay 7. The precoder 1 inverts the logical value of the output 5 only when the logical value of its input signal 4 is “1”, and maintains the logical value of the output when the logical value of its input signal is “0”. The logical value of the output 5, delayed by the one-bit delay 7 is fed back to an input of the XOR gate 10. Mathematically, the precoder 1 calculates the cumulative parity of the binary number input sequence 4.
The duobinary filter 2 separates the signal to two branches, one of the branches is delayed by a one-bit delay 8 and combined with another branch without delay at a summer 9. The output 6 of the duobinary filter 2 is usually loss-passed and sent to an external modulator in particular, and an optical modulation subsystem in general.
In the precoder 1 of FIG. 1, the preceding circuit has to operate in the same rate as the serial binary input 4. Problems generally occur for high data transmission rates, for example, 10-, 40-, 80-, 100-, and 160-Gb/s input signals. First, a high-speed XOR gate may not be available or may be quite expensive. Second, the realization of one-bit delay for the XOR gate is difficult. The one-bit delay 7 can utilize the propagation time of the feedback transmission line or can use a D-type flip-flop. If the propagation delay of the XOR gate 10 cannot be ignored compared with a time-slot of one bit due to the increase of the transmission rate, the delay time for the feedback to the XOR gate would become longer than one time-slot time.
Referring to FIG. 2, it is a block diagram illustrating the detailed configuration 20 of a conventional differential precoder as described in the prior art. For example, parallel precoding circuits are described in the European patent application of EP 1 026 863 A2 filed Mar. 2, 2000 and published Sep. 18, 2000, the paper of Yoneyama et al. (“Differential Precoder IC Modules for 20- and 40-Gbit/s Optical Duobinary Transmission Systems,” IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 12, November 1999, pp. 2263-2270), and the paper of K. Murata et al. (“Parallel precoder IC module for 40-Gbit/s optical duobinary transmission systems,” Electronics Letters, vol. 36, no. 18, Aug. 31, 2000, pp. 1571-1572). The circuit 20 of FIG. 2 uses a multiple input XOR gate 31 to calculate the parity of K sets of parallel data 30, followed by a differential circuit 33 similar to the precoder 1, a one-bit delay 37, and a ladder of XOR gates 32 to calculate each of the individual outputs 40. The multi-input XOR gate 31 is by itself a very complicated circuit, requiring many two-input logic gates. One implementation of the multi-input XOR gate can use a ladder of XOR gates. Another implementation of the multi-input XOR gate uses a tree of XOR gates. As shown in the papers of Yoneyama et al. and Murata et al., the circuit 20 requires elaborate circuit elements to align the timing of all K output data. For simplicity, the circuit elements for timing alignment are not shown in FIG. 2. In FIG. 2, the output of 40(K) has no gate delay but the output of 40(1) has (K−1) gate delays from the XOR gates of 10(K−1) to 10(1) in the ladder of XOR gates 32. As an indication of the difficulty, a four-input circuit in Yoneyama et al. requires two separate integrated circuits (ICs) occupied mostly by many electrical components used to compensate for gate delay. The requirement of timing alignment makes the prior parallel precoding circuits of EP1,026,863, Yoneyama et al., and Murata et al. for the parallel precoder very difficult to implement, especially for very large number of parallel inputs K.
Needed is a precoder design that can manage timing issues while accommodating large numbers of parallel inputs efficiently.